The present invention relates to electronic circuits, and more particularly, to techniques for providing reduced duty cycle distortion.
FIG. 1A illustrates a prior art delay line circuit used in a delay-locked loop (DLL) circuit. The delay line circuit of FIG. 1A includes 16 delay circuits 10-25 that are coupled in series and a 5-to-1 multiplexer circuit 50. Delay circuits 10-25 delay a reference clock signal REFCK. A counter control signal CCS controls the delays of the delay circuits 10-25. Multiplexer 50 selects a delayed version of the reference clock signal from the output of one of the delay circuits 15, 17, 19, 21, or 25 to generate a feedback clock signal FBCK based on the logic states of static select signals. The logic states of the static select signals remain constant during the operation of the DLL. FBCK is transmitted to a phase detector in the DLL.
Each of the delay circuits 10-25 includes the circuit architecture shown in FIG. 1B. FIG. 1B includes 1X delay circuits 101-108 and 2-to-1 multiplexer 110. Each of the delay circuits 101-108 includes a current starving inverter coupled in series with a standard CMOS inverter. Each of the current starving inverters in delay circuits 101-108 is a variable delay circuit that includes 9 PMOS transistors coupled in parallel and 9 NMOS transistors coupled in parallel. The PMOS and NMOS transistors can generate 9 different delay options for the current starving inverter.
Delay circuits 101-104 are coupled in series to delay the input clock signal at the Input of delay circuit 101 to generate a delayed clock signal at the high frequency input of multiplexer 110. Delay circuits 101-108 are coupled in series to delay the input clock signal at the Input of delay circuit 101 to generate a delayed clock signal at the low frequency input of multiplexer 110. Multiplexer 110 selects either the delayed clock signal at the low frequency input or the delayed clock signal at the high frequency input as an output clock signal at the Output based on the logic state of a static select signal. The logic state of the static select signal remains constant during the operation of the DLL. The delay options in delay circuits 101-108 are dynamically adjusted by the combination of a phase detector and counter circuit during operation of the DLL.